1. Field of the Invention
The present invention relates to a method and apparatus for refreshing synchronous dynamic random access memory in a system.
2. Art Background
Dynamic random access memory (DRAM) components provide an inexpensive solid state storage technology for today's digital systems. The digital information is maintained in the form of charge stored on a two dimensional array of capacitors. To access the DRAM array, a row address is provided (and held in a latch). This address selects one of the rows of the DRAM by selecting one of the word lines of the array. The other word lines are de-selected. In the case of a write operation, the contents of the column amplifiers are restored to the row of capacitors through the selected row of transistors. In the case of a read operation, the contents of the row of capacitors is sent through the selected row of transistors and the bit lines to the column amplifiers.
The sensing operation performed during a read operation is destructive, requiring the row of capacitors to be rewritten with a restore operation. The column amplifiers are latching so their contents are not destroyed when they are restored to the selected row of capacitors. The charge on each capacitor is not only destroyed during a sense operation, but is also steadily lost over time due to leakage mechanisms. This leakage current depends upon processing and operating conditions, so there is a variation from component to component as well as a variation between storage cells of a single component. The leakage current is also strongly dependent upon temperature (higher temperature causes higher leakage) and is weakly dependent upon the supply voltage used by the component. Because of the leakage, the storage cells must have their charge refreshed periodically. For example, the timing parameter t.sub.ref,max is used to denote the interval over which every cell must be read and written back at least once to guarantee proper data retention. An illustrative diagram of the internal structure of a DRAM is shown in FIGS. 1a and 1b.
There are two types of DRAMs: synchronous and asynchronous. In a synchronous DRAM, the time base is shared between the controller/processor and the DRAM component and is independent of the control signals sent to the DRAM. In an asynchronous DRAM, the control signals communicate the timing information in an asynchronous manner.
In a synchronous system, the DRAM may operate in a power down state. Power down is a state in which the component operates at lower power and does not operate synchronously because the internal clocks are not operating.
Refresh can be achieved a number of ways. In one method, referred to herein as an external process, the time base, which is the source of the timer for performing refresh, and the refresh row address counter are external to the DRAM. In a second method, referred to as an internal refresh process, both the time base and refresh row address counter are internal to the DRAM. In a third process referred to as a mixed refresh process, the time base is external and the refresh row address counter is internal to the DRAM.
FIG. 2 shows an asynchronous DRAM with external refresh and a memory system with the control, address and data wires which connect the DRAM to the processor or memory controller component. In this example, the DRAM uses an asynchronous interface. There are no clocks applied from the external system; the DRAM generates its own internal clocks when the control signals are pulsed. A read or write access begins by transmitting a row address on the address wires and by asserting the RAS control signal to latch the address inside the DRAM. The assertion of the row address causes the desired row to be sensed by the column amplifiers. After the assertion of the RAS control signal, the column address is transmitted on the multiplexed address wires and the CAS control signal is asserted so that the address is latched. This address selects the desired data word from the sensed row. This word is transmitted back to the processor or memory controller in the case of a read access. In the case of a write access, the information on the data wires is written into the column amplifiers and the modified row is restored back into the memory array. Typically a read access can be used to perform refresh operations, but is not optimal since it involves the transfer of a column address which is not utilized.
External refresh is typically achieved by transmitting only a row address and asserting RAS. This will cause the rows to be sensed and restored and can be done in a minimal amount of time. One drawback to external refresh is that it requires a count value identifying the current row being refreshed to be held in the processor or memory controller. Some types of asynchronous DRAMs with mixed refresh include a refresh address counter. A dedicated signal or a combination of existing signals (RAS, CAS) are used to cause a refresh of the row address in this counter and to increment the counter.
FIG. 3 shows a synchronous DRAM which is in a powered up state. The DRAM utilizes mixed refresh which includes the refresh address counter in the DRAM. While in the power up state, the synchronous DRAM can support either external or mixed refresh. Synchronous interfaces are desirable as information is transferred at a higher rate. However, synchronous interfaces also require more power than asynchronous interfaces. The power consumption increase is due to a clock signal which is received by the DRAM which dissipates AC power while it is running. The synchronous DRAMs use synchronous control signals to initiate a refresh of the row the address, which is located in the refresh address counter, just as in any asynchronous DRAM with a refresh address counter.
An important application area for DRAMs is in portable computing systems. This requires that the DRAMs are capable of holding information in storage cells for extended periods of time with minimal power consumption. The energy cost of powering up the synchronous interface to perform refresh is too high. One answer to these requirements is to provide internal refresh in a power down state. It is possible to disable the internal clock to avoid dissipating the synchronous interface power, but this prevents the synchronous signals from being used. A refresh address counter may be included in the DRAM along with an oscillator to drive it. When refresh mode is entered, the DRAM interface is powered down and only the oscillator operates. At periodic intervals, for example t.sub.ref,max /n.sub.row (where n.sub.row is the number of rows in the DRAM), the refresh address counter is incremented and the selected row is sensed and restored. A block diagram illustration of a synchronous DRAM with internal refresh in the power down state is shown in FIG. 4.
However, there are disadvantages with placing the oscillator inside the DRAM for the low power refresh mode. Typically this oscillator is implemented using transistors and capacitors with some coarse adjustment capability (e.g., using polysilicon programming fuses) at testing time. Such a circuit will produce a wide range of oscillator period across the range of processing conditions and a wide range of oscillator period across operating conditions, such as temperature and voltage. Further, the minimum refresh period, which the oscillator is attempting to duplicate, will produce a larger variation across processing conditions and an even larger, but more predictable variation with temperature. In practice, the t.sub.ref,max parameter is guaranteed by testing for all the storage cells at the worst case temperature for the DRAM. The maximum oscillator period parameter, t.sub.osc,max, is padded with sufficient margin such that t.sub.osc,max is less than t.sub.ref, max /n.sub.row. Thus, the following relationship must be satisfied: EQU t.sub.osc,min &lt;t.sub.osc,max &lt;t.sub.ref,max /n.sub.row.
As discussed above, the minimum oscillator period, t.sub.osc,min, value can be as much as three to ten times less than the t.sub.ref,max /n.sub.row value when the range of processing conditions and operating conditions are considered, indicating that the DRAM is refreshing more often than it needs to and therefore dissipating more power than necessary. Furthermore, the t.sub.ref,max value will typically increase by some geometric factor, for example, 2.times., for every 10.degree. drop in the ambient temperature. This means that in cooler systems the t.sub.ref,max value is higher making the mismatch between t.sub.osc,max and t.sub.ref,max in the above equation even greater.
At the system level, bringing the synchronous DRAM into and out of the power down state causes a latency to occur due to the need to synchronize the internal refresh mechanism with the synchronous interface.